With their favorable physical properties, nanowires have many potential uses in nanoscale-device applications. In semiconductor devices for example, nanowires are commonly used as building blocks for the fabrication of photonics and/or electronic nano devices. Nanowires may also be used in semiconductor devices to form connections, such as channels between the various electrodes of a transistor. The use of silicon nanowires has the added advantage of being easily integrated into existing silicon-based device technology and having reproducible control of the nanowires' electronic properties.
A top-down fabrication process is often used to produce devices that use silicon nanowires. The top-down fabrication process is similar to that used in the fabrication of complementary metal-oxide-semiconductor (CMOS) devices, and generally includes lithographically defining the nanowires in a silicon-on-insulator (SOI) wafer. In one implementation, the device formed contains silicon nanowires that span a well. Various processing steps may then be carried out from the top of the device. One such step is the thinning of parts of the nanowires that span the well, e.g., for the purpose of forming ultra-thin channels.
The thinning of the nanowires may be achieved by oxidation. For example, a hardmask can be deposited over portions of the nanowires that are not to be thinned by the oxidation. The hardmask has an open portion, called a window, through which oxidation of the select parts of the nanowires can take place.
Masking for selective oxidation at small dimensions can be challenging, as stress effects at edges tend to enhance the oxidation rate and create excessively oxidized regions in the nanowire. These regions are highly resistive and limit final nanowire dimensions, as thinning can physically disconnect the nanowire.
Control over the nanowire dimensions, such as the final nanowire diameter and aspect ratio, is important since variations in the geometry of the nanowire can induce corresponding variations in the device properties. To minimize variation, accurate control of both the pre-thinned silicon thickness on the SOI wafer (well beyond the few nanometer accuracy currently available) and of the lithographically defined nanowire width is needed.
One approach that can be used to improve aspect ratio uniformity of a thinned nanowire involves adjusting the lithographic dose to correct the nanowire's defined width based on local material thickness mapped with an ellipsometer. However, this approach does not provide sufficient accuracy since it is limited by the accuracy of the thickness measurement and lithographic control on the nanowire width. Self-limiting thermal oxidation may be used to reduce final nanowire size variations, but these processes are sensitive to initial nanowire asymmetry.
Therefore, fabrication processes for nanowire devices that avoid the problems associated with masking for selective nanowire oxidation would be desirable as would processes that provide for accurate control over the final nanowire dimensions in such devices.